Methods and devices for fault tolerant quantum gates
US11460876B1 · kind B1 · utility
3Cited by
2References
20Claims
0Family size
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Key dates
| Filing date | Jul 11, 2019 |
| Grant date | Oct 4, 2022 |
| Priority date | — |
| Expiry date | Mar 19, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N10/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method includes obtaining a plurality of entangled qubits, with high fault tolerance, represented by a lattice structure. The lattice structure includes a plurality of contiguous lattice cells. A first subset of the plurality of entangled qubits defines a first plane, and a second subset of the plurality of entangled qubits defines a second plane that is parallel to and offset from the first plane. The plurality of entangled qubits includes a defect qubit that is entangled with at least one face qubit on the first plane and at least one edge qubit on the second plane.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.