Memory device and memory system
US11461176B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 10, 2021 |
| Grant date | Oct 4, 2022 |
| Priority date | — |
| Expiry date | Aug 10, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/2906
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a multiphase clock generator which generates a plurality of divided clock signals, a first error correction block which receives a first divided clock signal among the plurality of divided clock signals, a first data multiplexer which transmits first least significant bit data corresponding to the first divided clock signal, a second error correction block which receives the first divided clock signal, and a second data multiplexer which transmits first most significant bit data corresponding to the first divided clock signal. The first error correction block receives the first least significant bit data and corrects a toggle timing of the first least significant bit data. The second error correction block receives the first most significant bit data and corrects a toggle time of the first most significant bit data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.