Hierarchical arbitration structure
US11461254B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 12, 2021 |
| Grant date | Oct 4, 2022 |
| Priority date | — |
| Expiry date | Apr 12, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0284
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus including a plurality of set arbitration circuits and a die arbitration circuit. The set arbitration circuits may each be configured to receive first commands and second commands and comprise a bank circuit configured to queue bank data in response to client requests and a set arbitration logic configured to queue the second commands in response to the bank data. The die arbitration circuit may be configured to receive the commands from the set arbitration circuits and comprise a die-bank circuit configured to queue die data in response to the client requests and a die arbitration logic configured to queue the second commands in response to the die data. Queuing the bank data and the die data for the second commands may maintain an order of the client requests and prioritize the first commands corresponding to a current controller over the first commands corresponding to a non-current controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.