Array substrate and manufacturing method thereof
US11462491B2 · kind B2 · utility
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2References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 25, 2018 |
| Grant date | Oct 4, 2022 |
| Priority date | — |
| Expiry date | Apr 9, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/931
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An array substrate and a manufacturing method thereof are provided. A plurality of groups of bonding terminals are formed on a substrate, a first electrostatic protection wire is formed on a marginal region of the substrate, and a second electrostatic protection wire is formed to connect the bonding terminals and the first electrostatic protection wire.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.