Three-dimensional semiconductor memory device with concave convex separation structures
US11462554B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 24, 2020 |
| Grant date | Oct 4, 2022 |
| Priority date | — |
| Expiry date | Apr 24, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device is disclosed. The device includes a peripheral circuit structure on a substrate, a semiconductor layer on the peripheral circuit structure, an electrode structure on the semiconductor layer, the electrode structure including electrodes stacked on the semiconductor layer, a vertical channel structure penetrating the electrode structure and being connected to the semiconductor layer, a separation structure penetrating the electrode structure, extending in a first direction, and horizontally dividing the electrode of the electrode structure into a pair of electrodes, an interlayered insulating layer covering the electrode structure, and a through contact penetrating the interlayered insulating layer and being electrically connected to the peripheral circuit structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.