Stacked semiconductor device, and set of onboard-components, body and jointing-elements to be used in the stacked semiconductor device
US11462668B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 30, 2020 |
| Grant date | Oct 4, 2022 |
| Priority date | — |
| Expiry date | Nov 30, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stacked semiconductor device encompasses a mother-plate having a mounting-main surface and a bottom-main surface, an onboard-element having a connection face facing to the mounting-main surface, a parent bump provided on the mother-plate, having a mother-site wall made of a layer of conductor, mother-site wall is perpendicular to the mounting-main surface, and a repair bump provided on the onboard-element at a side of the connection face, having a repair-site wall made of a layer of conductor having different hardness from the mother-site wall, the repair-site wall is perpendicular to the connection face, configure to bite each other with the parent bump at an intersection between the mother-site wall and the repair-site wall conductor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.