Systems and methods for wafer-level testing of transmitter-receiver links
US11463173B1 · kind B1 · utility
Inventors
Key dates
| Filing date | Jul 26, 2021 |
| Grant date | Oct 4, 2022 |
| Priority date | — |
| Expiry date | Jul 26, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02B6/4215
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An integrated transceiver chip comprising: a plurality of bidirectional ports; a plurality of grating couplers; a receiver having a first and a second input ports, the first input port being optically connected to a first grating coupler of the plurality of grating couplers, and the second input port being optically connected to a first bidirectional port of the plurality of bidirectional ports; and a transmitter having a first and a second input and a first and a second output ports, the first input port being optically connected to a second bidirectional port of the plurality of bidirectional ports and the second input port being optically connected to a second grating coupler, and the first output port being optically connected to a third bidirectional port of the plurality of bidirectional ports and the second output port being optically connected to a third grating coupler of the plurality of grating couplers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.