Programmable correlation computation system
US11463284B1 · kind B1 · utility
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4References
20Claims
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Key dates
| Filing date | Jul 9, 2021 |
| Grant date | Oct 4, 2022 |
| Priority date | — |
| Expiry date | Jul 9, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/03267
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Various embodiments described herein provide for a receiver device that includes a processor, a non-linear equalizer, an accumulation register, and a plurality of co-processors. Each of the plurality of co-processors is operably coupled to the processor, the non-linear equalizer, and the accumulation register. Each of the plurality of co-processors can be configured to receive a configuration value from the processor, receive a data signal for processing from the non-linear equalizer, process the data signal based on the configuration value, and provide at least a portion of the processed data signal to the processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.