Configurable memory architecture for computer processing systems
US11467742B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 4, 2021 |
| Grant date | Oct 11, 2022 |
| Priority date | — |
| Expiry date | Feb 4, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (IC) includes a memory manager having a plurality of memory ports, each configured to communicate with a corresponding floating memory block. The IC includes a first interconnect for a first domain, wherein the first interconnect has a first set of fixed ports configured to communicate with memory blocks dedicated to the first domain and a first set of floating ports configured to communicate with the memory manager, and a second interconnect for a second domain, wherein the second interconnect has a second set of fixed ports configured to communicate with memory blocks dedicated to the second domain and a second set of floating ports configured to communicate with the memory manager. The memory manager is configured to allocate a first portion of the memory ports to the first set of floating ports and a second portion of the memory ports to the second set of floating ports.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.