Selective erasure decoding for memory devices
US11467760B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 4, 2020 |
| Grant date | Oct 11, 2022 |
| Priority date | — |
| Expiry date | Apr 5, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/152
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, apparatuses, and corresponding techniques are described for selective erasure decoding on memory devices. Erasure decoding is performed on error correction codes (ECCs) read from memory locations associated with errors that are correctable through erasure decoding, as indicated by erasure information available to a memory controller or other device configured to decode ECCs. The erasure information can indicate locations within individual memory devices and, optionally, at different memory hierarchy levels. When the erasure information indicates that a location being read from is not associated with an error that is correctable through erasure decoding, regular error decoding is performed on ECCs read from such locations. Selective erasure decoding can be performed in connection with separate read operations that access different memory devices or a single read operation that accesses multiple memory devices concurrently.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.