Systolic array including fused multiply accumulate with efficient prenormalization and extended dynamic range
US11467806B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 27, 2019 |
| Grant date | Oct 11, 2022 |
| Priority date | — |
| Expiry date | Sep 11, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/4824
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods are provided to perform multiply-accumulate operations of normalized numbers in a systolic array to enable greater computational density, reduce the size of systolic arrays required to perform multiply-accumulate operations of normalized numbers, and/or enable higher throughput operation. The systolic array can be provided normalized numbers by a column of normalizers and can lack support for denormal numbers. Each normalizer can normalize the inputs to each processing element in the systolic array. The systolic array can include a multiplier and an adder. The multiplier can have multiple data paths that correspond to the data type of the input. The multiplier and adder can employ expanded exponent range to operate on normalized floating-point numbers and can lack support for denormal numbers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.