In-memory computing with cache coherent protocol
US11467834B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2020 |
| Grant date | Oct 11, 2022 |
| Priority date | — |
| Expiry date | Sep 10, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0026
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system for computing. In some embodiments, the system includes: a memory, the memory including one or more function-in-memory circuits; and a cache coherent protocol interface circuit having a first interface and a second interface. A function-in-memory circuit of the one or more function-in-memory circuits may be configured to perform an operation on operands including a first operand retrieved from the memory, to form a result. The first interface of the cache coherent protocol interface circuit may be connected to the memory, and the second interface of the cache coherent protocol interface circuit may be configured as a cache coherent protocol interface on a bus interface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.