Executing cross-core copy instructions in an accelerator to temporarily store an operand that cannot be accommodated by on-chip memory of a primary core into a secondary core
US11467836B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 26, 2021 |
| Grant date | Oct 11, 2022 |
| Priority date | — |
| Expiry date | Jan 26, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/045
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An acceleration unit including a primary core and a secondary core is provided. The primary core includes a first on-chip memory, a primary core sequencer adapted to decode a received first cross-core copy instruction, and a primary core memory copy engine adapted to acquire a first operand from a first address in the first on-chip memory and copy the acquired first operand to a second address in a second on-chip memory of the secondary core. Further, the secondary core includes a second on-chip memory, a secondary core sequencer adapted to decode a received second cross-core copy instruction, and a secondary core memory copy engine adapted to acquire the first operand from the second address in the second on-chip memory and copy the acquired first operand back to the first address in the first on-chip memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.