Low-latency packet processing for network device
US11467998B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 16, 2021 |
| Grant date | Oct 11, 2022 |
| Priority date | — |
| Expiry date | Mar 16, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/7807
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques for low-latency packet processing are disclosed. A network device receives a first set of write transactions including a first set of data segments corresponding to a first DMA descriptor from a host. The network device receives a second set of write transactions including a second set of data segments corresponding to a second DMA descriptor from the host. The network device detects that the first set of data segments have been written. In response to detecting that the first set of data segments have been written, and prior to completely writing the second set of data segments and to receiving a packet notifier from the host, the network device processes the first DMA descriptor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.