Deep neural network processor with interleaved backpropagation
US11468332B2 · kind B2 · utility
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Key dates
| Filing date | Nov 13, 2017 |
| Grant date | Oct 11, 2022 |
| Priority date | — |
| Expiry date | Apr 13, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/048
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Processing circuitry for a deep neural network can include input/output ports, and a plurality of neural network layers coupled in order from a first layer to a last layer, each of the plurality of neural network layers including a plurality of weighted computational units having circuitry to interleave forward propagation of computational unit input values from the first layer to the last layer and backward propagation of output error values from the last layer to the first layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.