Gate driver and display apparatus including the same
US11468853B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 30, 2021 |
| Grant date | Oct 11, 2022 |
| Priority date | — |
| Expiry date | Jul 30, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2340/0435
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A gate driver includes a first stage, a second stage, a third stage and a fourth stage. The first stage includes a first clock terminal receiving a first clock signal, a second clock terminal receiving a second clock signal, a carry terminal receiving a vertical start signal and an output terminal outputting a first gate output signal. The second stage includes a first clock terminal receiving the second clock signal, a second clock terminal receiving the first clock signal, a carry terminal receiving the vertical start signal and an output terminal outputting a second gate output signal. The third stage includes a first clock terminal receiving the second clock signal, a second clock terminal receiving the first clock signal, a carry terminal receiving the first gate output signal and an output terminal outputting a third gate output signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.