Semiconductor device including a spacer in contact with an upper surface of a silicide layer
US11468919B2 · kind B2 · utility
0Cited by
7References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 7, 2020 |
| Grant date | Oct 11, 2022 |
| Priority date | — |
| Expiry date | Jun 22, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/485
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device is provided. The semiconductor device includes a substrate a bit line structure disposed on the substrate, a trench adjacent to at least one side of the bit line structure, a storage contact structure disposed within the trench, and comprising a storage contact, a silicide layer, and a storage pad which are stacked sequentially. A spacer structure is disposed between the bit line structure and the storage contact structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.