System and method for detecting memory cell disturbance by monitoring canary cells
US11468942B2 · kind B2 · utility
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2References
18Claims
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Key dates
| Filing date | Mar 2, 2021 |
| Grant date | Oct 11, 2022 |
| Priority date | — |
| Expiry date | Mar 2, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2211/4068
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One embodiment provides a memory module. The memory module includes a plurality of rows of memory cells, with a respective row comprising one or more canary memory cells that are more susceptible to disturbance than non-canary memory cells, and a disturbance-detection circuit coupled to at least one canary memory cell of a corresponding row and configured to output a control signal in response to the disturbance to the canary memory cell exceeding a predetermined threshold.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.