Semiconductor chip package and fabrication method thereof
US11469152B2 · kind B2 · utility
1Cited by
1References
18Claims
0Family size
Assignee
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Key dates
| Filing date | Sep 29, 2020 |
| Grant date | Oct 11, 2022 |
| Priority date | — |
| Expiry date | Jan 22, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3512
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor chip package includes a substrate having a top surface and a bottom surface, and a semiconductor device mounted on the top surface of the substrate. A gap is provided between the semiconductor device and the top surface of the substrate. A pre-cut laminate epoxy sheet is disposed on the top surface of the substrate and around a perimeter of the semiconductor device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.