ESD-protection device and MOS-transistor having at least one integrated ESD-protection device
US11469222B2 · kind B2 · utility
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18Claims
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Key dates
| Filing date | Mar 30, 2020 |
| Grant date | Oct 11, 2022 |
| Priority date | — |
| Expiry date | Mar 30, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/115
Abstract
Protection against electrostatic discharges is to be improved for electronic devices, or is to be provided in the first place. The device for protection against electrostatic discharges having an integrated semiconductor protection device comprises an inner region (1) configured at least as a thyristor (SCR) and at least one outer region (2a, 2b) configured as a corner region, which is formed and configured at least as a PNP transistor. The inner region (1) and the at least one outer region (2a, 2b) are arranged adjacent to one another.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.