Method for decoding inertia-effect bit-flip LDPC codes
US11469775B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 4, 2021 |
| Grant date | Oct 11, 2022 |
| Priority date | — |
| Expiry date | Mar 4, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/1108
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method for decoding a Low Density Parity Check code. At each decoding iteration, as long as the syndrome of the estimated word indicates an error, a set ({tilde over (F)}) of the least reliable bits of the word is determined as those where the value of a local energy function ({tilde over (E)}n) is less than a threshold value. The local energy value of a bit includes a first component proportional to the correlation between this bit and a sample corresponding to the observed signal, a second component representing the number of non-satisfied constraints wherein the bit acts, and a third component decreasing with the number (n) of iterations made since the last flipping of this bit. The bits of the estimated word belonging to this set are flipped, where applicable with a predetermined probability, to provide a new estimated word at the following iteration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.