Offset correction in high-speed serial link receivers

US11469928B2 · kind B2 · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventors

• Ani Xavier · Kanchinakote, IN
• Jagannathan Venkataraman · Bengaluru, IN
• Nagalinga Swamy Basayya Aremallapur · Ranebennur, IN
• Aviral Singhal · Bengaluru, IN
• Arun Mohan · Bengaluru, IN
• Rakesh Manjunath · Bengaluru, IN
• Aravind Ganesan · Bengaluru, IN
• Harshavardhan Adepu · Bengaluru, IN

Key dates

• Filing date: Jun 30, 2021
• Grant date: Oct 11, 2022
• Expiry date: Jun 30, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H04L25/4917
• WIPO field: Digital communication
• WIPO sector: Electrical engineering

Abstract

A receiver circuit comprising an equalizer and a method of correcting offset in the equalizer. In an example, the equalizer includes a plurality of delay stages for sampling and storing a sequence input samples, and a plurality of coefficient gain stages, each coupled to a corresponding delay stage to apply a gain corresponding to a coefficient value. The outputs of the coefficient gain stages are summed to produce a weighted sum for quantization by a slicer. Offset correction circuitry is provided, including memory storing a look-up table (LUT) for each coefficient gain stage, each storing offset correction values corresponding to the available coefficient values for the coefficient gain stage. Addressing circuitry retrieves the offset correction values for the coefficient values currently selected for each gain stage, and applies an offset correction corresponding to the sum of the retrieved offset correction values.