System-on-chip including network for debugging
US11470018B2 · kind B2 · utility
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Key dates
| Filing date | Aug 30, 2019 |
| Grant date | Oct 11, 2022 |
| Priority date | — |
| Expiry date | Aug 15, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0772
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
Provided is a system-on-chip. A central controller is configured to, in response to a request from a host, generate a first signal for requesting error information related to an error from a design of an IP. A local controller is configured to generate a second signal including the error information of the target IP if the request from the host is determined to be for the target IP based on the first signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.