Laterally offset parallax barriers in multi-view display
US11474372B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 17, 2020 |
| Grant date | Oct 18, 2022 |
| Priority date | — |
| Expiry date | Dec 17, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K59/12
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, an apparatus includes a multi-view display that includes several pixels. The apparatus includes a parallax barrier that overlays the several pixels of the multi-view display. The parallax barrier includes several barrier rows that are arrayed in a first dimension, where each barrier row includes several barriers arrayed in a second dimension. Each of the barriers are separated from adjacent barriers in the barrier row by an aperture. Each barrier row is offset from adjacent barrier rows by a macro offset distance in the second dimension. A portion of each barrier is offset by a micro offset distance in the second dimension, where the micro offset distance is smaller than the macro offset distance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.