Circuit for providing clock to de-serializer in communication physical layer
US11474554B2 · kind B2 · utility
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7References
18Claims
0Family size
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Key dates
| Filing date | Jan 12, 2021 |
| Grant date | Oct 18, 2022 |
| Priority date | — |
| Expiry date | Feb 5, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0814
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit is provided for providing a sampling clock to de-serializers in a communication physical layer. The circuit includes a slave delay lock loop (DLL), to receive an input clock and provide the sampling clock to the de-serializers. Further, a master DLL is included for receiving the input clock and outputting a control signal to the slave DLL to adjust a delay amount of the sampling clock of the slave DLL. The master DLL replicates a circuit of the slave DLL with a loop detection and determines the control signal for output.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.