Multichip timing synchronization circuits and methods
US11474557B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 15, 2020 |
| Grant date | Oct 18, 2022 |
| Priority date | — |
| Expiry date | Jan 11, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N5/02
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, the present disclosure includes multichip timing synchronization circuits and methods. In one embodiment, hardware counters in different systems are synchronized. Programs on the systems may include synchronization instructions. A second system executes synchronization instruction, and in response thereto, synchronizes a local software counter to a local hardware counter. The software counter on the second system may be delayed a fixed period of time corresponding to a program delay on the first system. The software counter on the second system may further be delayed by an offset to bring software counters on the two systems into sync.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.