Emulator synchronization subsystem with enhanced slave mode
US11474844B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2020 |
| Grant date | Oct 18, 2022 |
| Priority date | — |
| Expiry date | Apr 15, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F8/41
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments described herein include an emulator system having a synchronization subsystem comprising devices, organized in logical hierarchy, controlling synchronization of a system clock and system components during emulation execution. The devices of the logical hierarchy communicate bi-directionally, communicating status indicators upwards and execution instructions downwards. A TCI is designated “master TCI” and others are designated “slave TCIs.” The master TCI asserts a RDY status that propagates upwards to a root node for a number cycles. The slave TCIs execute in “infinite run” and continually assert the RDY status upwards to the root device regardless of the cycle count. The root node detects each RDY status and propagates downwards a GO instruction to the master TCI and the slave TCIs. In this way, the TCIs execute until the master TCI de-asserts RDY status. The result is only the master TCI is manipulated to, for example, start/stop emulation or perform iterative execution.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.