Computing device and operation method thereof
US11474937B2 · kind B2 · utility
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22Claims
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Key dates
| Filing date | Nov 20, 2020 |
| Grant date | Oct 18, 2022 |
| Priority date | — |
| Expiry date | Dec 17, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17728
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computing device and an operation method thereof are provided. The computing device includes multiple memories and an indexer circuit. The indexer circuit is separately coupled to the memories through multiple memory channels. The indexer circuit determines an arrangement of at least one lookup table to at least one of the memories according to a characteristic of the at least one lookup table and a transmission bandwidth of the memory channels, so as to balance a transmission load of the memory channels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.