Artificial reality system with inter-processor communication (IPC)
US11474970B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 24, 2019 |
| Grant date | Oct 18, 2022 |
| Priority date | — |
| Expiry date | Oct 24, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N13/344
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
The disclosure describes techniques for interrupt and inter-processor communication (IPC) mechanisms that are shared among computer processors. For example, an artificial reality system includes a plurality of processors; an inter-processor communication (IPC) unit comprising a register, wherein the IPC unit is configured to: receive a memory access request from a first processor of the processors, wherein the memory access request includes information indicative of a hardware identifier (HWID) associated with the first processor; determine whether the HWID associated with the first processor matches an HWID for the register of the IPC unit; and permit, based on determining that the HWID associated with the first processor matches the HWID for the register of the IPC unit, the memory access request to indicate a communication from the first processor to at least one other processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.