System and method for correction of memory errors
US11475170B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 28, 2019 |
| Grant date | Oct 18, 2022 |
| Priority date | — |
| Expiry date | Jan 12, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2209/34
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A self-correcting memory system comprising an integrated circuit including memory and memory content authentication functionality, which is operative to compare content to be authenticated to a standard and to output “authentic” if the content to be authenticated equals the standard and “non-authentic” otherwise; and error correction functionality which is operative to apply at least one possible correction to at least one erroneous word entity in said memory, yielding a possibly correct word entity, call said authentication for application to the possibly correct word entity, and if the authentication's output is “authentic”, to replace said erroneous word entity in said memory, with said possibly correct word entity thereby to yield error correction at a level of confidence derived from the level of confidence associated with the authentication.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.