Method and system for designing an integrated circuit, and an integrated circuit
US11475198B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 13, 2021 |
| Grant date | Oct 18, 2022 |
| Priority date | — |
| Expiry date | Jan 13, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer-implemented method for designing a floorplan for an integrated circuit includes determining a circuit design for the integrated circuit, wherein the circuit design for the integrated circuit has a system device and a logic device. Logical definitions for the system device and the logic device are determined. A plurality of interconnect devices are determined. A plurality of interconnect figures of merit (FOMs) associated with the plurality of interconnect devices are also determined. The method includes determining, with an optimization operation, a candidate floorplan for the circuit design based upon the logical definitions for the system device, the logic device, the plurality of interconnect devices, and the interconnect FOMs for the interconnect devices. The candidate floorplan is determined based upon parameters associated with computational performance, power consumption, and physical area of the candidate floorplan for the circuit design. The candidate floorplan is implemented as the integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.