Circuit layout techniques
US11475200B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 4, 2020 |
| Grant date | Oct 18, 2022 |
| Priority date | — |
| Expiry date | Jun 4, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/3953
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Various implementations described herein are directed to an apparatus having a processor and memory having instructions stored thereon that, when executed by the processor, cause the processor to identify conductive paths in a physical layout of an integrated circuit having nodal features that define a connective structure of the integrated circuit. The instructions may cause the processor to traverse the conductive paths to detect valid metals and redundant metals. The valid metals may refer to valid conductive paths between the nodal features that conjoin the nodal features. The redundant metals may refer to unused conductive paths that provide disjointed paths from the nodal features. The instructions may cause the processor to indicate the valid metals as marked with a first indicator and to indicate the redundant metals as unmarked with a second indicator that is different than the first indicator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.