Storage unit and static random access memory
US11475943B2 · kind B2 · utility
0Cited by
22References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 9, 2021 |
| Grant date | Oct 18, 2022 |
| Priority date | — |
| Expiry date | Apr 9, 2041 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A storage unit includes a latch, and the latch provides a first storage bit. The storage unit further includes a first MOS transistor. A gate of the first MOS transistor is connected to the first storage bit, a source of the first MOS transistor is connected to a first read line, and a drain of the first MOS transistor is connected to a second read line. In a first state, the first read line is a read word line, and the second read line is a read bit line; or in a second state, the second read line is a read word line, and the first read line is a read bit line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.