Semiconductor memory with data protection function and data protection method thereof
US11475963B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 19, 2021 |
| Grant date | Oct 18, 2022 |
| Priority date | — |
| Expiry date | Apr 8, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3418
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory and a data protection method are provided. The semiconductor memory includes a memory array, a switch circuit, a control circuit and a power-down monitor circuit. The switch circuit is coupled to the memory array. The control circuit is coupled to the switch circuit. The power-down monitor circuit is coupled to the control circuit and a supply voltage. The power-down monitor circuit is configured to determine whether that the supply voltage drops below a first power-down detect level during a programming period, to output a trigger signal to the control circuit. The control circuit executes a reset sequence of the semiconductor memory according to the trigger signal. The first power-down detect level is lower than a minimum value of the supply voltage recorded in a datasheet of the semiconductor memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.