Fuse lines and plugs for semiconductor devices
US11476190B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2016 |
| Grant date | Oct 18, 2022 |
| Priority date | — |
| Expiry date | Jan 2, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/532
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments herein describe techniques for fuse lines and plugs formation. A semiconductor device may include a fuse line having a nominal fuse segment abutted to a necked fuse segment. The nominal fuse segment may be wider than the necked fuse segment. A first spacer may be along a first side of the fuse line and a second spacer along a second side opposite to the first side of the fuse line. The first spacer may include a part having a width at least twice a width of a part of the second spacer. A plug within a vicinity of the necked fuse segment may have a plug width that may be at least twice a plug with of a plug of an interconnect line outside the vicinity. Other embodiments may also be described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.