Integrated circuit including memory cell and method of designing the same
US11476257B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 9, 2021 |
| Grant date | Oct 18, 2022 |
| Priority date | — |
| Expiry date | Jul 9, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/501
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes: a first wiring layer on which a first bit line pattern and a positive power supply pattern, a first power supply line landing pad, and a first word line landing pad are formed; a second wiring layer on which a first negative power supply pattern connected to the first power supply line landing pad, and a first word line pattern connected to the first word line landing pad are formed; a third wiring layer on which a second negative power supply pattern connected to the first negative power supply pattern, and a second word line landing pad connected to the first word line pattern are formed; and a fourth wiring layer on which a second word line pattern, connected to the second word line landing pad, are formed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.