Contact resistance reduction employing germanium overlayer pre-contact metalization
US11476344B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 10, 2021 |
| Grant date | Oct 18, 2022 |
| Priority date | — |
| Expiry date | Dec 10, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Techniques are disclosed for forming transistor devices having reduced parasitic contact resistance relative to conventional devices. The techniques can be implemented, for example, using a standard contact stack such as a series of metals on, for example, silicon or silicon germanium (SiGe) source/drain regions. In accordance with one example such embodiment, an intermediate boron doped germanium layer is provided between the source/drain and contact metals to significantly reduce contact resistance. Numerous transistor configurations and suitable fabrication processes will be apparent in light of this disclosure, including both planar and non-planar transistor structures (e.g., FinFETs), as well as strained and unstrained channel structures. Graded buffering can be used to reduce misfit dislocation. The techniques are particularly well-suited for implementing p-type devices, but can be used for n-type devices if so desired.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.