Techniques for phase shift reduction in a single crystal multiple output clock system
US11480992B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 21, 2021 |
| Grant date | Oct 25, 2022 |
| Priority date | — |
| Expiry date | Jan 21, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/40
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Certain aspects of the present disclosure provide a circuit for clock signal generation. The circuit generally includes a plurality of clock generation circuits configured to generate a plurality of clock signals from a clock signal, and a power supply circuit having an output coupled to power supply inputs of the plurality of clock generation circuits. The circuit may also include a capacitor array coupled to the output of the power supply circuit and include a plurality of capacitive elements, the capacitor array being configured to selectively couple each of the plurality of capacitive elements to the output of the power supply circuit based on a quantity of one or more active clock generation circuits of the plurality of clock generation circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.