Memory module adapted to implementing computing functions
US11482264B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2021 |
| Grant date | Oct 25, 2022 |
| Priority date | — |
| Expiry date | Dec 22, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/109
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present description concerns a memory device (200) comprising: a memory circuit (201) implementing operations and performing elementary operations including a reading, a writing, or a computing operation; a control circuit (205) receiving instructions from a processor (231), and breaking down each received instruction into a plurality of elementary operations to generate an elementary operation request flow; a circuit (203) of direct data transfer from or to said memory circuit (201), the transfer circuit (203) receiving instructions from the processor (231), breaking down each received instruction into a plurality of elementary operations to be performed in said memory circuit to generate an elementary operation request flow; an internal data exchange link (204) directly coupling said memory circuit (201) to the direct transfer circuit (203); and an arbitration circuit (309).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.