Planarization method of a capping insulating layer, a method of forming a semiconductor device using the same, and a semiconductor device formed thereby
US11482448B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 2020 |
| Grant date | Oct 25, 2022 |
| Priority date | — |
| Expiry date | Apr 27, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/27
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Semiconductor devices and methods of forming the same are provided. The methods may include forming a stacked structure that may include a stacking area and a stepped area and may include first layers and second layers alternately stacked. The second layers may have a stepped shape in the stepped area, and the stepped area may include at least one flat area and at least one inclined stepped area. The methods may also include forming a capping insulating layer covering the stacked structure. The capping insulating layer may include a first capping region having a first upper surface and a second capping region having a second upper surface at a lower level than the first upper surface. The methods may further include patterning the capping insulating layer to form protrusions at least one of which overlaps the stepped area and then planarizing the capping insulating layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.