Memory and fabrication method thereof
US11482488B2 · kind B2 · utility
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18Claims
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Key dates
| Filing date | Feb 24, 2020 |
| Grant date | Oct 25, 2022 |
| Priority date | — |
| Expiry date | Jun 20, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a memory is provided. The method includes providing a bit-line layer, on a semiconductor substrate and having bit lines arranged in the bit-line layer; providing a shielding layer, on the bit-line layer and having a conductive shielding structure arranged in the shielding layer. The conductive shielding structure is within a top-view projection area of the bit lines and is grounded. The method further includes providing a word-line layer, on the shielding layer and having word lines arranged in the word-line layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.