Semiconductor package having molding member and heat dissipation member
US11482507B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 12, 2020 |
| Grant date | Oct 25, 2022 |
| Priority date | — |
| Expiry date | Mar 26, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15311
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a package substrate, a first semiconductor chip disposed on the package substrate, at least one second semiconductor chip disposed on a region of an upper surface of the first semiconductor chip, a heat dissipation member disposed in another region of the upper surface of the first semiconductor chip and at least a region of an upper surface of the second semiconductor chip, and having an upper surface in which at least one trench is formed, and a molding member covering the first semiconductor chip, the second semiconductor chip, an upper surface of the package substrate, and side surfaces of the heat dissipation member, and filling the at least one trench while exposing the upper surface of the heat dissipation member.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.