Multiple clock domain alignment circuit
US11483007B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 23, 2021 |
| Grant date | Oct 25, 2022 |
| Priority date | — |
| Expiry date | Jul 7, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/74
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Described are apparatus and methods to calibrate and align multiple high-speed clock domains. A system includes at least two clock domains, a launch circuit connected to each of the at least two domains, and a calibration circuit. Each clock domain including a resettable device having a local reset retime clock. The launch circuit aligns a reset pulse with the local reset retime clock by using a launch clock from one of the domains, where the reset pulse is incoherent with respect to the domains, adjusts a delay of the launch clock to control a launch time of the reset pulse, and sends the reset pulse based on the delayed launch clock. The calibration circuit samples a local reset retime delayed clock to generate a readback signal. The launch circuit and the calibration circuit iterate through selected delays until safe arrival timing is indicated from each readout.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.