Bitline control supporting binning mode for pixel arrays with phase detection autofocus and image sensing photodiodes
US11483502B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 4, 2021 |
| Grant date | Oct 25, 2022 |
| Priority date | — |
| Expiry date | Jun 4, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/78
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An imaging device includes a pixel array including pixel circuits arranged into rows and columns. Each bitline of a plurality of bitlines is coupled to a respective column of pixel circuits of the pixel array. The plurality of bitlines is grouped into pairs of bitlines. A plurality of binning circuits is coupled to the plurality of bitlines. Each binning circuit is coupled to a respective pair of bitlines and is responsive to a multi-mode select signal. Each binning circuit is configured to output a binned signal responsive to the first and second bitlines of the respective bitline pair in a first mode. Each binning circuit is configured to output a first signal from a first bitline of the respective bitline pair in a second mode. Each binning circuit is configured to output a second signal from the second bitline of the respective bitline pair in a third mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.