Digital serial read-out architecture
US11483510B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 21, 2021 |
| Grant date | Oct 25, 2022 |
| Priority date | — |
| Expiry date | Jul 10, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N25/42
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Techniques are described for implementing read-out architectures to support high-speed serialized read-out of a large number of digital bit values, such as for high-resolution pixel conversions in CMOS image sensor applications. For example, outputs from a large number of digital data sources (e.g., counters) are coupled with transmission gates of the read-out architecture, and the transmission gates are sequentially enabled, thereby shifting in bit data from the data sources one at a time. The transmission gates are grouped into gate groups. For each gate group, embodiments seek balance total path delay across the gate groups by controlling clock and data path delays to be inversely related, and ensuring that total path delays for all gate groups are within a single clock period. Some embodiments include a partitioned bus for further gate group-level control over the path delay and data bus capacitance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.