Instruction cache behavior and branch prediction
US11487542B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 20, 2020 |
| Grant date | Nov 1, 2022 |
| Priority date | — |
| Expiry date | Jul 20, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/452
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Instruction cache behavior and branch prediction are used to improve the functionality of a computing device by profiling branching instructions in an instruction cache to identify likelihoods of proceeding to a plurality of targets from the branching instructions; identifying a hot path in the instruction cache based on the identified likelihoods; and rearranging the plurality of targets relative to one another and associated branching instructions so that a first branching instruction that has a higher likelihood of proceeding to a first hot target than to a first cold target and that previously flowed to the first cold target and jumped to the first hot target instead flows to the first hot target and jumps to the first cold target.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.