Inter-die interrupt communication in a seamlessly integrated microcontroller chip
US11487685B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 8, 2021 |
| Grant date | Nov 1, 2022 |
| Priority date | — |
| Expiry date | May 8, 2041 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques in electronic systems, such as in systems comprising a CPU die and one or more external mixed-mode (analog) chips, may provide improvements advantages in one or more of system design, performance, cost, efficiency and programmability. In one embodiment, the CPU die comprises at least one microcontroller CPU and circuitry enabling the at least one CPU to have a full and transparent connectivity to an analog chip as if they are designed as a single chip microcontroller, while the interface design between the two is extremely efficient and with limited in number of wires, yet may provide improved performance without impact to functionality or the software model.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.