Memory processing unit architecture
US11488650B2 · kind B2 · utility
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24Claims
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Key dates
| Filing date | Apr 6, 2020 |
| Grant date | Nov 1, 2022 |
| Priority date | — |
| Expiry date | Apr 6, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C13/0004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory processing unit architecture can include a plurality of memory regions and a plurality of processing regions interleaved between the plurality of memory regions. The plurality of processing regions can be configured to perform computation functions of a model such as an artificial neural network. Data can be transferred between the computation functions in respective memory processing regions. In addition, the memory regions can be utilized to transfer data between a computation function in one processing region and a computation function in another processing region adjacent to the given memory region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.