Semiconductor device and method
US11489053B2 · kind B2 · utility
0Cited by
17References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 9, 2020 |
| Grant date | Nov 1, 2022 |
| Priority date | — |
| Expiry date | Apr 9, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0133
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In an embodiment, a device includes: a gate electrode; a epitaxial source/drain region adjacent the gate electrode; one or more inter-layer dielectric (ILD) layers over the epitaxial source/drain region; a first source/drain contact extending through the ILD layers, the first source/drain contact connected to the epitaxial source/drain region; a contact spacer surrounding the first source/drain contact; and a void disposed between the contact spacer and the ILD layers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.