Forming 3D transistors using 2D van per waals materials

US11489064B2 · kind B2 · utility

Assignee

• TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD. · TW

Inventors

• Sheng-Kai Su · Shanghai, CN
• Jin Cai · Hubei, CN

Key dates

• Filing date: May 26, 2020
• Grant date: Nov 1, 2022
• Expiry date: Jun 20, 2040

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/258

Abstract

A method includes etching a dielectric layer to form a dielectric fin, depositing a transition metal dichalcogenide layer on the dielectric fin, and performing an anisotropic etching process on the transition metal dichalcogenide layer. Horizontal portions of the transition metal dichalcogenide layer are removed, and vertical portions of the transition metal dichalcogenide layer on sidewalls of the dielectric fin remain to form a vertical semiconductor ring. The method further includes forming a gate stack on a first portion of the two-dimensional semiconductor vertical semiconductor ring, and forming a source/drain contact plug, wherein the source/drain contact plug contacts sidewalls of a second portion of the vertical semiconductor ring.